Analog and RFIC Layout

In doing layouts for digital circuits, the speed and the area are the two most important issues. In contrast, in doing layout for analog circuits, everything should be considered simultaneously. In addition to the speed and the area, other equally critical considerations should be taken into account.
For example, for amplifier design, good matching in devices is necessary to minimize the offset voltage, and good shielding is required to protect critical nodes from being disturbed. Without proper layout, the mismatches and the coupled noise would be quite large and would significantly degrade the performance of the amplifiers.


Analog layout Issues

Matching of Devices:
Matching of individual devices is of paramount concern in analog circuit design. Infact almost all of the 'analog layout techniques' are actually methods for improving matching between different devices on a chip. Matching is important because most analog circuit designs use a ratio based design technique(e.g. current mirrors). Some common techniques that help improve device mathcing are MULTI-GATE FINGER LAYOUT and COMMON-CENTROID LAYOUT.

Noise:
Noise is important in all analog circuits because it limits dynamic range. In general there are two types of noise, random noise and environmental noise. Random noise refers to noise generated by resistors and active devices in an integrated circuit; environmental noise refers to unwanted signals that are generated by humans. Two common examples of environmental noise are switching of digital circuits and 60 Hz 'hum'. In general, random noise is dealt with at the circuit design level. However the are some layout techniques which can help to reduce random noise. MULTI-GATE FINGER LAYOUT reduces the gate resistance of the poly-silicon and the neutral body region, which are both random noise sources. Generous use of SUBSTRATE PLUGS will help to reduce the resistance of the neutral body region, and thus will minimize the noise contributed by this resistance.

Enivironmental noise is also dealt with at the circuit level. One common design technique used to minimize the effects of environmental noise is to employ a 'fully-differential' circuit design, since environmental noise generally appears as a common-mode signal. However SUBSTRATE PLUGGING is also very useful for reducing 'substrate noise', which is a particularly troublesome form of environmental noise encountered in highly integrated mixed-signal systems and Systems-On-a-Chip (SOC). Substrate noise occurs when a large amount digital circuits are present on a chip. The switching of a large number of circuits discharges large dynamic currents to the substrate, which cause the substrate voltage to 'bounce'. The modulation of the substrate voltage can then couple into analog circuits via the body effect or parasitic capacitances. SUBSTRATE PLUGGING minimizes substrate noise because it provides a low impedance path to ground for the noise current.

Note:
Issues that are important in digital circuits are still important in analog layout. Foremost among these is parasitic aware layout. It is important to minimize series resistance in digital circuits because it slows switching speed. Series resistance also slows analog circuits, plus it introduces unwanted noise. Parasitic capacitance is avoided in digital circuits because it slows switching speed and/or increases dynamic power dissipation. Stray capacitance has the same effect in analog circuits (bias current must be increased to maintain bandwidth and/or slew rate when extra load capacitance is present) plus it can lead to instability in high gain feedback systems.

Common error reduction technique :
Use large area to reduce random error
Common Centroid layout to reduce linear gradient errors
Use unit element arrays
Interdigitize for matching
Use of symmetry of photolithographic invariance
Controlled edge or corner effects
Dummy device for similar vicinity
Guard rings for isolation
Careful floor planning, More details


• Lecture notes MOS Capacitances, Passive Components, and Layout
  
  
• Matching of Resistors and Capacitors
  
  
• Good introduction on tanner tool includes device modelling
  
  
• lecture notes2 ,classes.yale.edu
  
  
• lecture notes3, uta.edu Semiconductor Device Modeling and Characterization
  
  
• Cadence tutorials with inverter example
  
  
• lecture notes4 from iastate.edu
  
  
• OP AMP layout
  
  
• introduction for layout in cadence tool, includes device matching
  
  
• From engineering.ucsb.edu
  
  
• lecture notes from stanford.edu
  
  
• Analog integrated circuit design methodology
  
  
• Lectures in Analog layout
  
  
• Automatic Layout of Analog and Digital systems
  
  
• Layout Issues in Analog Mixed Signal ICs
  
  
• Layout considerations
  
  
• Layout with cadence
  
  
• Links to Information on Advanced Layout Topics
  
  
• The analog layout array
  
  CMOS Technology :
  • Flow varies with process types & company
  – N-Well CMOS
  – Twin-Well CMOS
  • Start with substrate selection
  – Type: n or p
  – Doping level, ?resistivity
  – Orientation, 100, or 101, etc
  – Other parameters
  
  
  
• cmos technology
  
  What is BiCMOS?
  
  BiCMOS technology combines Bipolar and CMOS transistors onto a single integrated circuit where the advantages of both can be utilized.
  
• bicmos process
  
  failure mechanisms
  
  Failure Modes
  
  • Thermal Secondary breakdown – high power, small
  junction causes junction melting
  
  • Metallization Melt – ESD causes the metal to melt and bond wires to fuse, usually causes and open circuit
  • Dielectric Breakdown – high potential difference across a dielectric region cause a punch through
  • Bulk Breakdown – changes in junction parameters caused by excessive temperature at the junction
  
  
• failure mechanism
  What is Charge Spreading?
  
  Charge spreading is the mechanism underlying the formation of channels.
  
  It requires the presence of static electric charges at the insulating interface.
  
  These charges consists primarily of electrons.
  
  Hot carrier injection also contributes to charge spreading along with integrated circuits that do not produce hot carriers. http://forum.rficdesign.com/Attachments/charge_spreading.zip">charge spreading
  
  capacitors in vlsi
  • Coupling AC Signals
  • Constructing timing networks
  • Constructing phase shift networks
  • Feedback loop compensation
  
• cmos capacitors
  Matching of Resistors and Capacitors
  
  
  
• matching of passive devices
  
  effect of temp in vlsi
  The concept:
  – Temperature variations cause variations in
  the resistance of the resistor
  • Consider the following:
  – Tj=Ta+Pd?ja
  – Tj=Tc+Pd? jc
  • Tj=junction temp, Ta=ambient temp,
  Tc=case temp, Pd=power dissipation,
  junction-to-ambient thermal impedance
  
  
• effect of temperatures
  
  OPAMP Layout
  
  
• cmos operational amplifier layout The example shows here is the layout and verification of the most important building block in analog integrated circuit operational amplifier.
  the steps are follows ( Only layout discussion not circuit design )
  A. Enter Schematic
  B. Pre-layout Simulation Using Spectre
  C. Custom Layout Using Virtuoso
  D. Extraction and LVS
  E. Post-Layout Simulation Using Spectre
  A. Schematic
  

  

  Figure 1. Complete OTA Schematic
  Free download of cmos model files from mosis.org
  
• CMOS model Files from mosis both new and old technologies
  
  
  
  
  Analog IC and layout Design Software
  
  
• Cadence www.cadence.com
  
  
• Mentor Graphics www.mentor.com
  
  
• Tanner Tools www.tanner.com
  
  
• RF Design Environment from agilent
  
  
• Stabie-Soft
  
  
• Magic The original layout editor. Free
  
  
• LASI free layout editor for windows
  
  
• WinVLSI free layout editor tool for windows
  
  
  

  Some analog layout Issues

  MULTI-GATE FINGER LAYOUT refers to implementing a single, wide transistor as several narrow transistors in parallel. This minimizes the gate resistance and it also makes it easier to match the transistor with other devices. When referring to a multiple gate finger device one usually uses the term 'M-factor' to refer to the number of gate fingers. Therefore an M=4 device has 4 gate fingers.
  
  Note: When trying to ratio two or more devices you should always use the same unit transistor size for each device and then include multiple gate fingers to achieve the desired ratio. For instance, a current mirror containing a 10/2 and 5/2 device is NOT a perfect ratio of two because of oxide encroachment. However a 5/2 M=2 device and a 5/2 M=1 device is a perfect ratio of two.
  
  COMMON-CENTROID LAYOUT refers to a layout style in which a set of devices has a common center point. This is used to minimize the effect of linear process gradients (e.g. oxide thickness) in a circuit.
  Example: Consider that a transistor 'A' has 'M' fingers and can be represented by 'M' instances of the letter 'A'. For example 'AAAA' represents a transistor 'A' that has 4 fingers.
  Now consider the layout of two transistors, 'A' and 'B'.
  One structure is: AABB
  The problem with this structure is that the transistor 'A' will have a different oxide capacitance (which affects transconductance, Ft) than 'B' because of oxide gradients. For instance, if the oxide thickness at the center of the structure is Tox, and there is an oxide gradient DEL, the average oxide thickness for 'A' and 'B' is
  Tox(A, average) = [Tox - 2DEL]/2 + [Tox - DEL]/2 = Tox - 3DEL/2
  Tox(B, average) = [Tox + 2DEL]/2 + [Tox + DEL]/2 = Tox + 3DEL/2
  Now consider the following layout: ABBA
  The average oxide thickness will now be:
  Tox(A, average) = [Tox - 2DEL]/2 + [Tox + 2DEL]/2 = Tox
  Tox(B, average) = [Tox - DEL]/2 + [Tox + DEL]/2 = Tox.
  Many other common centroid layout structures are possible:
  ABCCBA, ABBBBA, ...
  Also in two dimensions:
  AB BA OR ABAB BABA ABAB BABA
  
  
  SUBSTRATE PLUGGING simply refers to making an ohmic contact to the substrate. This technique is used in digital circuits to minimize latch-up. In analog circuits it is used to minimize latch-up and for the reasons discussed above.