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Transmitter and Receiver
Tutorial, Research papers, Lecture notes, Free download, faq, thesis, Resources, .....
- Wireless link loss ; link budget for wireless networks
- GSM transceiver ; Specifications by Chris Rudell of berkeley
- GPS receiver article by Derek Schaeffer, Stanford
- overview of GSM ; John Scourias
- frequency planning spreadsheet, excell sheet
- class notes , with Mathcad routines
- GSM Handset ; commsdesign.com
- transceiver design , arrl.org
- estimating Dynamic Range for WCDMA
- transceiver design ; bessercourse.com
- WCDMA Transceiver
- Single-chip CMOS FM radio receiver
- Radio propagation models
- design of rf amplifier
- emitter degeneration feed back amplifier
- feed back amplifier
- small signal amplifier
- buffer categories
Transceiver Design Tools
- Amplitude Modulation
- Superheterodyne Spectrum Analyzer
- GBPPR ; calculator from qsl.net
- J.C. Rudell, J.J. Ou, R. S. Narayanaswami, G. Chien, J.A. Weldon,
L. Lin, K.C. Tsai, L. Tee, K. Khoo, D. Au, T. Robinson,
D. Gerna, M. Otsuka, and P. R. Gray,
" Recent Developments
in High Integration Multi-Standard CMOS
Transceivers for Personal Communication Systems ,"
- Jacques C. Rudell, Jia-Jiunn Ou, Thomas Cho, George Chien,
Francesco Brianti, Jeffrey A. Weldon and Paul R. Gray,
"
A 1.9GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless
Telephone Applications,"
(PDF) Journal of Solid State Circuits,
- J.Rudell, JJ. Ou, T.Cho, G.Chien, F.Brianti, J.Weldon, and P.Gray,
"
A 1.9GHz Wide-Band IF Double Conversion CMOS Integrated Receiver
for Cordless Telephone Applications
Digest of Tehnical Papers, International Solid-State Circuits Conference,
San Francisco,
br>
- "
Recent Developments in High Integration Multi-Standard CMOS
Transceivers for Personal Communication Systems ,"(PDF)
J.C. Rudell, J.J. Ou, R. S. Narayanaswami, G. Chien, J.A. Weldon,
L. Lin, K.C. Tsai, L. Tee, K. Khoo, D. Au, T. Robinson,
D. Gerna, M. Otsuka, and P. R. Gray,
Invited paper at the International Symposium on Low Power Electronics,
Monterey, California.
- "
A 1.9GHz Wide-Band IF Double Conversion CMOS Integrated Receiver for Cordless
Telephone Applications (GIF/MIF/PS)," J.Rudell, JJ. Ou, T.Cho, G.Chien,
F.Brianti, J.Weldon, and P.Gray. Presentation for the 1997 International
Solid-State Circuits Conference Feb. 8th, 1997
- K. Onodera, P. Gray,
"A 75-mW 128-MHz DS-CDMA Baseband Demodulator for High-Speed Wireless
Applications" (166k PDF), IEEE J. Solid-State Circuits
- K. Onodera, P. Gray,
"A 75mW 128MHz DS-CDMA Baseband Correlator for High-Speed Wireless
Applications" (31k PDF), 1997 VLSI Circuit Symposium
- J. Rudell,
"A 50MHz 8-tap Adaptive Equalizer for Partial Response Channel , JSSC
- J. Rudell,
"A 50MHz 70mW 8-tap Adaptive Equalizer/Viterbi Sequence
Detector in 1.2um CMOS," (PS/MIF/HTML) CICC, June 1994.
- M. Tsai, "CMOS Power
Amplifiers for Wireless Communications"
(PDF) UC Berkeley PhD Thesis, 2007.
- J. Weldon, "High-Performance
CMOS Transmitters for Wirelesss Communications"
(PDF) UC Berkeley PhD Thesis, 2005.
- R. S. Narayanaswami, "RF
CMOS Class C Power Amplifiers for Wireless Communications"
(PDF) UC Berkeley PhD Thesis, December 2001.
- N. Sneed,
"A 2-GHz CMOS LC-Tuned VCO using Switched-Capacitors to Compensate
for Bond Wire Inductance Variation"
(PDF) UC Berkeley MS Thesis, December 2000.
- G. Desjardins,
"Adapative Digital Signal Processing Algorithms for
Image-Rejection Mixer Self-Calibration"
(PDF) UC Berkeley MS Thesis, December 2000.
- L. Lin, "
Design Techniques of High Performance Integrated Frequency
Synthesizer for Multi-standard Wireless Communication Applications"
(PDF) UC Berkeley PhD Thesis, November 2000.
- G. Chien,
"Low-Noise Local Oscillator Design Techniques using a DLL-based
Frequency Multiplier for Wireless Applications"
(PDF) UC Berkeley PhD Thesis, January 2000.
- D. Au,
"Programmable, Low Noise, High-Linearity Baseband Filter for a
Fully-Integrated, Multi-standard, CMOS RF Receiver"
(PDF) UC Berkeley MS Thesis, January 1999.
- R. S. Narayanaswami,
"The Design of a 1.9GHz 250mW CMOS Power Amplifier For DECT"
(PDF) UC Berkeley MS Thesis, May 1998.
- T. Weigandt,
"Low-Phase-Noise, Low-Timing-Jitter
Design Techniques for Delay Cell Based VCOs and Frequency
Synthesizers"
(PDF) UC Berkeley PhD Thesis, January 1998.
- C. J. Barrett,
"Low-Power Decimation Filter Design
for Multi-Standard Transceiver Applications"
(PDF) UC Berkeley MS Thesis, December 1997.
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Analogue
Filters
10-MHz 60-dB Dynamic-Range 4th-Order Butterworth Lowpass
Filter
Cheung D., Hong Kong Univ. of Science &
Technology
A 1GHz, 40 mW Fully Integrated
Continuous-Time Second-Order Bandpass Filter in GaAs Technology
Moughabghab R., Rockwell
Semiconductor Systems
A High-Q Bandpass Fully Differential SC Filter with Enhanced
Testability
Vįzquez D., University of
Sevilla
A Low-Voltage Power and Area Efficient BiCMOS Log-Domain
Filter
Punzenberger M., Swiss Federal Inst. of
Technology
High-Accuracy Charge-Redistribution Switched-Capacitor Video
Bandpass Filter in Standard 0.8 µm CMOS
Quinn P.J.,
Philips Semiconductors
Realization of a 10 MHz integrated bipolar DECT band-pass
filter
Wassenaar R.F., University of
Twente
CAD
An ISM band Transceiver Chip for Digital
Spread Spectrum Communication
Moffat M., GEC Plessey
Semiconductors Inc.
Constructing High Level Macrocell Models using the Shlaer-Mellor
Method
Whipp D., GEC Plessey
Semiconductors
Data
Conversion
200 Megasample per second 6 bit A/D
converter
Leuthold O., GEC Plessey
Semiconductors
A 15-bit 2MHz Nyquist Rate delta-sigma ADC in a 1 µm CMOS
Technology
Marques A., Katholieke Universiteit
Leuven
A 16 bit 500ks/s 2.7V 5mW ADC/DAC in 0.8um CMOS using
error-correcting successive approximation
Schofield W.G.,
Fujitsu Microelectronics Ltd.
A 1V CMOS fully-differential switched-opamp bandpass simga-delta
modulator
Baschirotto A., Universitą di
Pavia
A 2.5MHz 55dB Switched-Current Bandpass sigma-delta Modulator for
AM Signal Conversion
de la Rosa J.M., Inst. de
Microelectrónica Sevilla
A 200 MHz cell for a Parallel-Successive-Approximation ADC in 0.8
µm CMOS, using a Reference Pre-Select scheme
Eklund J.-E.,
Linköping University
A 5-bit 150 MS/s, 3.3 V CMOS A/D Converter
with a 32 Step Adjustable Reference Circuit
Desel
Th., Fraunhofer-Institute
A 74dB Dynamic Range, 1.1-MHz Signal Band 4th-Order 2-1-1 Cascade
Multi-Bit CMOS sigma-delta Modulator for ADSL
Medeiro F.,
Inst. de Microelectrónica Sevilla
A Low-Voltage, High-Speed and Low-Power Full Current-Mode
Video-rate CMOS A/D Converter
Sugimoto Y., Chuo
University
REMBRANDT: A RF ASIC for DECT TDMA
applications
van Zeijl P.T.M., Ericsson Business Mobile
Networks
Single Bit Sigma-Delta Modulator with Nonlinear Quantization for
µ-Law Coding
Weiler D.,
Fraunhofer-Institute
Digital
Architectures
A Full-Custom Self-Timed DSP Processor
Implementation
Laiho M., Tampere University of
Technology
A High Speed, Low Power 8-Tap Digital FIR Filter for PRML
Disk-Drive Read Channels
Ki H.-J., Korea
University
A Low Noise Folded Bit-Line Sensing Architecture for Multi-Gb DRAM
with Ultra High Density 6F² Cell
Kim J.-S., Seoul
National University
A Low-Power Low-Voltage Digital Bus Interface for MCM-Based
Microsystems
Correia J.H., Delft University of
Technology
A Low-Power, High-Speed 0.25 µm GaAs
D-FF
Enomoto T., Chuo
University
Hierarchical N-Port Memory Architecture based on 1-Port Memory
Cells
Mattausch H.J., Hiroshima
University
Implementation of a 5x5 trits multiplier in a Quasi-Adiabatic
Ternary CMOS Logic
Mateo D., Univ. Politčcnica de
Catalunya
Low-Power 200 Msps, Area Efficient, 5-Tap Programmable FIR
Filter
Moloney D., Silicon Systems Design
Ltd.
Rapid design of complex DSP cores
McCanny
J.V., The Queen's University of Belfast
Reduced complexity two-phase micropipeline latch
controller
Taylor G.S., The University of
Edinburgh
Digital
Comms Ccts
10 Gb/s Single-Chip Data Regeneration with
an Injection Synchronised Ring Oscillator and an Automatic Phase
Adjustment
Wang Z.-G.,
Fraunhofer-Institute
2.5 Gb/s ATM Physical Layer Controller in 0.8 µm
BiCMOS
Salama C.A.T., University of
Toronto
A 3.3 V 350 MHz 0.35 µm CMOS Programmable RIF Based on Redundant
Coding in a Bit Plane Architecture
Thorel P.,
France Telecom
A 3.3V Power Adaptive 1244 / 622 / 155 Mb/s
TRANSCEIVER for ATM, SONET/SDH
Belot D.,
SGS-Thomson
Multilevel Decoder-Decision Circuit for High Bitrate ETDM
Transmission
Desrousseaux P., France
Telecom
Robust CMOS Compander
Hossack D., Wolfson
Microelectronics Ltd.
LF
Analogue (Return to
Overwiew)
A -90 dB THD Rail-to-Rail input opamp using
a new local charge pump in CMOS
Duisters A.F., Philips
Research Laboratories
A 3.3 Volt, low distortion ISDN line driver with a novel quiescent
current control circuit
Casier H., Alcatel
Mietec
A CMOS Chopper Opamp with Integrated Low-Pass
Filter
Bakker A., Delft University of
Technology
A Novel 1.5-V CMOS Operational
Amplifier
Palmisano G., Universitą di
Catania
A Wide Range dB-linear Variable Gain CMOS
Amplifier
Gräfe M., Universität
Dortmund
Embedded 5V-to-3.3V Voltage Regulator for Supplying Digital IC“s
in 3.3V CMOS Technology
den Besten G.W., Philips
Research Laboratories
Low-power low-voltage chopped transconductance amplifier for noise
and offset reduction
Sanduleanu M.A.T., University of
Twente
Logic
Circuits
A 1V Bootstrapped CMOS Digital Logic
Family
Choe S.Y., The University of New South
Wales
A High Speed SRAM macro for 0.35 µm Low Voltage SOI/CMOS Gate
Arrays
Nii K., Mitsubishi Electric
Corporation
A novel driver architecture capable of driving high capacitive
loads for sub-half-micron technologies
Bouras I., NCSR
"Demokritos"
High Speed Arithmetic Design Using CPL and DPL
Logic
Brewer B., Analog Devices Newbury Design
Centre
New Two Single-Port GaAs Memory Cell
Bernal
A., TIMA Laboratory
Novel High-Speed and Low-Power Dynamic MOS
Flip-Flops for a Low-Power 1.25GHz Multiplexer/Demultiplexer
Kanno H., NEC
Corporation
Novel Level-Identifying Circuit for Flash Multi-Level
Memories
Montanari D., IMEC
Practical Low Power Design Architecture for 256 Mb
DRAM
Tanizaki T., Mitsubishi Electric
Corporation
Mixed Sig
Systems
A 1mW only Wireless Phone Voiceband D to A
CODEC
Moeneclaey N., Texas Instruments
France
A Fully-Integrated CMOS AM Radio Receiver for Wrist-watch
Calibration
Op't Eynde F., Mixed Silicon
Structures
A Fully-Integrated FM Discriminator for RDS
Applications
Nitescu-Henry A., IEMN
A Robust Analogue Interface System for Sub-Micron CMOS Video
DSP
Redman-White W., Philips
Semiconductors
A Variable Gain Transimpedance Amplifier Channel with a Timing
Discriminator for a Time-of-Flight Laser Radar
Palojärvi
P., University of Oulu
Low-Power Offset-Calibrated CMOS I/Q
Transmit Interface for Portable CommunicationsGoes
J., Instituto Superior Técnico
R, G, B acquisition interface with line locked clock generator,
for LCD driver
Marie H., Philips
Semiconductors
Read front end of a new AC coupled Preamplifier for 300 Mb/s Hard
Disk Drives using single stripe Magneto Resistive heads
Punch
F., Philips Composants et Semiconduct.
Modelling
& Matching (Return to
Overwiew)
An EEPROM in a Standard CMOS
technology
Op't Eynde F., Mixed Silicon
Structures
Drain Current Mismatch in SOI CMOS Current Mirrors and D/A
Converters due to Localised Internal and Coupled
Heating
Tenbroek B., University of
Southampton
FET Mobility Degradation and Device Mismatch due to Packaging
Induced Die Stress
Jaeger R.C., Auburn
University
Mismatch Modelling for Large Area MOS
Devices
Grünebaum U., Universität
Dortmund
Neural
& Fuzzy
A 0.9V, 30µW Feature Extractor for Remote
Speech Recognition
Borgatti M., University of
Bologna
A 12bit Medium-Time Analog Storage Device in a CMOS
Standard-Process
Ehlert M., Technical University of
Berlin
Building Blocks for Low-Power Stochastic Pulse Coded
Systems
Naess S., University of
Oslo
Performance enhancement in stochastic pulse code systems using
parallelism and redundancy
Naess S., University of
Oslo
Oscillators & PLLs
1-V Low-Noise 200 MHz Relaxation Oscillator
Deval Y., Université
Bordeaux
A 1.2µ BiCMOS realization of a low power and offset-free
Voltage/Frequency converter
Zhang M.,
IXL-ENSERB
A 3-V delay-modulated PLL synthesizer for analog FM
transmitters
Rahkonen T., University of
Oulu
A Direct Digital Synthesizer with an On-chip
D/A-converter
Vankka J., Helsinki University of
Technology
A lower ISM band frequency synthesizer and GMSK data
modulator
Filiol N.M., Carleton
University
A wide band Tuning System for Fully Integrated Satellite
Receivers
Vaucher C.S., Philips Research
Laboratories
A Wide-Tunable Translinear Second-Order
Oscillator
Serdijn W. A., Delft University of
Technology
Accurate Simulation of Phase Noise in
Oscillators
De Smedt B., Katholieke Universiteit
Leuven
CMOS circuit technique for serial IC interconnection up to 1.1
Gb/s
Lares R., University of Ulm
Integrated RF transmitter based on SAW
Oscillator
Heuberger A.,
Fraunhofer-Institute
RF
Analogue
1.25 Gb/s CMOS Differential Transimpedance
Amplifier for Gigabit Networks
Yoon T., Univ. of
California at Los Angeles
A 0.9V 960MHz CMOS Radio Front End Employing a Doubly Balanced
Transconductance Mixer
Xavier B.A., Hughes Network
Systems
A 103MHz Open-Loop Full CMOS Highly -Linear
Sample-and-Hold Amplifier
Hadidi Kh., Urmia
University
A Direct Conversion IC for Digital Satellite
TV
Blaud P., Deutsche Thomson-Brandt
GmbH
A Generic CAD Model for Arbitrarily Shaped and Multi-Layer
Integrated Inductors on Silicon Substrates
Papananos Y.,
National Technical Univ. of Athens
A Low-Voltage CMOS Downconversion Mixer for RF
Applications
Svelto F., Universitą di
Pavia
An IF-Strip with Integrated 2nd IF Filter for a Triple Conversion
GPS Receiver
Piazza F., ETH Zurich
The Impact of Scaling Down to Deep-Submicron on CMOS RF
Circuits
Huang Q., Swiss Federal Inst. of
Technology
Sensor
Interfaces
A 0.5mW Passive Telemetry IC for Biomedical
Applications
Huang Q., Swiss Federal Inst. of
Technology
A 5V CMOS Chip for Interpolation of Sine/Cosine
Signals
Krauss M., Zentrum Mikroelektronik Dresden
GmbH
A 9-channel Time-to-Digital Converter for an Imaging Lidar
Application
Mäntyniemi A., University of
Oulu
A Current-Mode ASIC for Use with Position Sensitive Detector
Arrays
Hatfield J.V., UMIST
A High Resolution Electron Imaging
Integrated Circuit
Hatfield J.V.,
UMIST
A High Resolution Time-to-Digital Converter Based on
Time-to-Voltage Interpolation
Räisänen-Ruotsalainen E.,
University of Oulu
A Resistance Variation Tolerant Constant Power Heating Circuit for
Integrated Sensor Applications
Chan S.S.W., Hong Kong
Univ. of Science & Techn.
A Switched Current, Switched Capacitor Temperature Sensor in 0.6u
CMOS
Tuthill M., Analog Devices
CMOS Photosensor Arrays with On-Chip Signal
Processing
Schanz M., Gerhard-Mercator Univ. of
Duisburg
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