VLSI Design

• VLSI CAD EDUCATIONAL SITES
  
  
• VHDL projects
  
  
• PLD Links
  
  
• COMPUTER AIDED VLSI DESIGN(E-book)
  
  
• Index: VHDL, Verilog and SystemC Simulation Tools from Blue Pacific.
  
  
• Download VHDL Similulator
  
  
• VHDLInternational [VI]
  
  
• Abstracts DAC 96
  
  
• x84labs
  
  
• 33rd Design Automation Conference Proceedings
  
  
• SIGDA's DAC Page
  
  
• SIGDA Proceeding Archives
  
  
  
• ACM Digital Library Search
  
  
• Synplicity: Home
  
  
• FPGA Information
  
  
• The FPGA Database
  
  
• The RPM Project: Hardware Emulation of Multiprocessor Systems
  
  
• RPM Project: Papers & Technical Reports
  
  
• GSRC People
  
  
• ResearchIndex: The NECI Scientific Literature Digital Library
  
  
• ResearchIndex good research papers from nec
  
  
• Rapid Hardware Prototyping On RPM-2: Methodology And Experience - Dubois, Jeong, Song, Moga (ResearchIndex)
  
  
• The British Library
  
  
• Welcome to the ALIA home page
  
  
• VLSI CAD PAPERS
  
  
• University of Illinois at Urbana-Champaign
  
  
• http://www-scf.usc.edu/~jaeheonj/pub.html
  
  
• Scott Hauck - UWEE Faculty
  
  
• Logic Partitioning
  
  
• Multi-FPGA Systems & Rapid-Prototyping
  
  
• Publications
  
  
• Research
  
  
• ACM Digital Library: International Symposium on Field Programmable Gate Arrays
  
  
• Index of /pubs/contents/proceedings/series/
  
  
• JRD Tata Memorial Library OPAC Search Engine
  
  
• Virtual Wires
  
  
• Virtual Wires Published Papers
  
  
• Doulos HDL Associates ( Tutorial)
  
  
• ALDEC, Inc. (Tutorial)
  
  
• SILOS III from Simucad (Free simulator)
  
  
• Verilogger Pro from SynaptiCAD Inc. ( Free simulator)
  
  
• SMASH from Dolphin Integration (Free simulator)
  FREE VLSI TOOLS on the NET

  
  
  • Berkeley Spice [ 3f5 rpm
    
  • Alliance VHDL
    
  • Ver Structural Verilog Compiler
    
  • VERIWELL : A verilog Simulator
    
  • MAGIC Layout Tool
    
  • SUPREM II
    
  • SUPREM III
    
  • SUPREM-IV.GS
    
  • PISCES
    
  • PISCES IIb
    
  • PISCES-2ET
    
  • PISCES 2H-B
    
  • MINIMOS 6.0
    
  • CALTECH - Chipmunk System
    
  • Ptolemy II (Ptolemy II is a set of Java packages supporting heterogeneous, concurrent modeling and design.)

  VERILOG Links
  
  
  • Verilog On-Line Tutorial, by Dr. Daniel Hyde
    
  • Verilog On-Line Mannual, by Prof. Gerrard Blair
    
  • Verilog Introduction for Digital Design
    
  • Rajesh Bawankule's Verilog and EDA Page
    
  • Alternate Verilog FAQ.
    
  • Celia's Verilog & EDA page
    
  • Project VeriPage (PLI resources)
    
  • Veripool: Public domain verilog resources

  VHDL Links

  
  
  • Begining VHDL: Class Notes by Zainalabedin Navabi, Northeastern University.
    
  • VHDL Code Land (VCL) Page.
    
  • VHDL International Home Page
    
  • VHDL International Users Forum (VIUF)
    
  • VHDL Validation Home Page
    
  • FAQ comp.lang.vhdl
    
  • VHDL Models

  Microprocessor / Microcontroller

  
  
  • Great Microprocessors
    
  • CPU Central, Uncensored
    
  • Computer Design, OnLine
    
  • Intel Microprocessors
    
  • Intel Architechture Lab's
  
  Site information
  Tutorial, Research papers, Lecture notes, Design Issues, Free download software, Wireless, RF, RFIC, Analog integrated circuit, vlsi, asic, electrnics, engineering, components, design tools, spice, circuit diagram, schematic, consultant, capacitor, inductor, nmos, pmos, parasitic, modelling, radio frequency, Design, Microwave,UHF, VHF, MMIC, MEMS,schematics, Module, Modem, Antenna, Transceiver, Receiver, Transmitter, Bluetooth, analog, circuit, integrated circuit, impedance, matching, transmission line, bandgap, pll, DLL, phase locked loop, tool, pll design, spurious analysis, mixer, products, calculator, wlan system level design impedance matching, technical, rfcmos, interview questions and answers, rf design, hr interview, verilog, vhdl, veriloga, lna, antenna, definition, synthesis, timing analysis, asic FAQ, vlsi design, technology, Design flow, ips, design, job, career, semiconductor, Analog , Mixed signal, CMOS process, cmosrf, rfcmos, silicon, Wireless Design, UWB, circuit, ic design, analysis, frequently asked question, design problems, ieee paper, layout issues, design techniques, device modelling, defintions, eda board, forum, 3G, HSDPA, UMTS, GPS, GSM, GPRS, ph.d. thesis, operational amplifier, vlsi forum, analog layout, Education, university, institute, research groups, project, Forum, noise, Resources,
  
  
  
  
  
  -EDA BOARD- http://forum.rficdesign.com
  
  -RF DESIGN- http://rf.rficdesign.com
  
  -Resources and links- http://links.rficdesign.com
  
  

  Good research papers from DAC conference

  TUTORIAL 1) ESL Design Methodology Using SystemC
  Organizer: Francine Bacchini - ThinkBold Corporate Communications, San Jose, CA
  Speakers: Wolfgang Rosenstiel - Univ. of Tuebingen, Tubingen, Germany
  Jack Donovan - ESLX, Inc., Austin, TX
  Maurizio Vitale - Philips Semiconductors, Pittsburgh, PA
  Laurent Maillet-Contoz - STMicroelectronics, Crolles, France
  Mike Meredith - Forte Design Systems, San Jose, CA
  Vincent Viteau - Summit Design, Inc., Cedex, France
  
  TUTORIAL 2) Practical Aspects of Coping with Variability: An Electrical View
  Organizer: Chandu Visweswariah - IBM Corp., Yorktown Heights, NY
  Speakers: Xi-Wei Lin - Synopsys, Inc., Mountain View, CA
  Bora Nikolic - Univ. of California, Berkeley, CA
  Peter A. Habitz - IBM Corp., Burlington, NC
  Riko Radojcic - Qualcomm CDMA Technologies, San Diego, CA
  
  TUTORIAL 3) Real DFM Solutions, Tools, Methodologies, and Successes
  Organizer: Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA
  Speakers: Nagaraj NS - Texas Instruments Inc., Dallas, TX
  Jean-Pierre Schoellkopf - STMicroelectronics, Crolles, France
  Mike Smayling - Applied Materials, Sunnyvale, CA
  Ban P. Wong - Chartered Semiconductor, Milpitas, CA
  Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA
  
  TUTORIAL 4) Surviving and Thriving in the World of Chip and Package Co-Design
  Organizers: Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA
  Howard Chen - IBM Corp., Yorktown Heights, NY
  Speakers: David Flynn - ARM Ltd., Cambridge, UK
  Paul Harvey - IBM Corp., Austin, TX
  Howard Chen - IBM Corp., Yorktown Heights, NY
  Lei He - Univ. of California, Los Angeles, CA
  Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA
  Kaushik Sheth - Rio Design Automation, Inc., Santa Clara, CA
  
  TUTORIAL 5) - SystemVerilog: Language Tutorial and Industrial Verification Experience
  Organizer: Johny Srouji - IBM Corp., Austin, TX
  Speakers: Johny Srouji - IBM Corp., Austin, TX
  Karen Pieper - Synopsys, Inc., Sunnyvale, CA
  Tom Fitzpatrick - Mentor Graphics Corp., Groton, MA
  John Havlicek - Freescale Semiconductor, Inc., Austin, TX
  Matt Maidment - Intel Corp., Portland, OR
  Cliff Cummings - Sunburst Design Inc., Portland, OR
  
  TUTORIAL 6) Tools for Hybrid Embedded Systems: Modeling, Verification, and Design
  Organizer: Luca Carloni - Columbia Univ., New York, NY
  Speakers: Hilding Elmqvist - Dynasim AB, Lund, Sweden
  George Pappas - Univ. of Pennsylvania, Philadelphia, PA
  Pieter J. Mosterman - The MathWorks, Inc., Natick, MA
  Alessandro Pinto - Univ. of California, Berkeley, CA
  Alberto Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA
  
  TUTORIAL 7) From Basic to Advanced Techniques for Silicon Debug and Diagnosis
  Organizer: Srikanth Venkataraman - Intel Corp., Hillsboro, OR
  Speakers: Srikanth Venkataraman - Intel Corp., Hillsboro, OR
  Miron Abramovici - DAFCA Inc., Framingham, MA
  Robert Aitken - ARM, Sunnyvale, CA
  
  
  
  

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  -DISCUSSION - http://forum.rficdesign.com -RF DESIGN-

  1 PANEL: How Will the Fabless Model Survive?
  2 Special Session: Why Doesn't My System Work?
  3 Hierarchical Synthesis for Mixed-Signal Designs
  4 Processor and Communication Centric SoC Design
  5 Practical Applications of DFM
  6 PANEL: The IC Nanometer Race: What Will It Take to Win?
  7 Special Session: Bridging the System to RTL Verification Gap
  8 Leakage, Power Analysis and Optimization
  9 MPSoC Design Methodologies and Applications
  10 Statistical Timing Analysis
  11 PANEL: Entering the Hot Zone -- Can You Handle the Heat and Be Cool?
  12 Special Session: Reliability Challenges for 65nm and Beyond
  13 Power Grid Analysis and Design
  14 Advances in Formal Solvers
  15 Gate Modeling and Model Order Reduction
  16 Special Session: MPSoC Design Tools
  17 Special Session: Highlights of ISSCC: Multimedia
  18 Buffer Insertion
  19 Testing and Validation for Timing Defects
  20 Advanced Topics in Processor and System Verification
  21 Software for Real-Time Applications
  22 PANEL: Building a Standard ESL Design and Verification Methodology: Is It J
  23 Invited Session: CAD Challenges for Leading-Edge Multimedia Designs
  24 Routing
  25 The Test Bin
  26 PANEL: Variation-Aware Analysis: Savior of the Nanometer Era?
  27 Low Power and Ultra-Low Voltage Design
  28 High-Level Exploration and Optimization
  29 PANEL: Design Challenges for Next-Generation Multimedia, Game and Entertai
  30 CAD for FPGAs
  31 Secure Systems
  32 Logic Synthesis 1
  33 Low-Power, Thermal-Aware Architectures
  34 Low Power System Level Design
  35 Power-Constrained Design for Multimedia
  36 Electrical and Thermal Issues in FPGAs
  37 Special Session: Beyond Low-Power Design: Environmental Energy Harvesting
  38 Communication-Driven Synthesis
  39 Parallelism and Memory Optimizations
  40 PANEL: Tomorrow's Analog: Just Dead or Just Different?
  41 Nanotubes and Nanowires
  42 Simulation Assisted Formal Verification
  43 Yield Analysis and Improvement
  44 Approaches to Soft Error Mitigation
  45 Design/Technology Interaction
  46 PANEL: Building a Verification Test Plan: Trading Brute Force for Finesse
  47 Special Session: More Moore's Law and More than Moore's Law
  48 Formal Specification and Verification Testbench Generation
  49 Analysis and Optimization Issues in NoC Design
  50 Special Session: Key Technologies for Beyond the Die
  51 Analog Design and Design Assistance
  52 High-Performance Simulation of Transaction Level and Dataflow Models
  53 Nano- and Bio-Chip Design
  54 Logic and Sequential Synthesis
  55 Low Power Circuit Design
  56 Beyond-the-Die Circuit and System Integration
  57 New Ideas in Analog/RF Modeling and Simulation
  58 Advanced Methods for Interconnect Extraction, Clocks and Reliability
  59 PANEL: DFM Where's the Proof of Value?
  60 Bounded Model Checking and Equivalence Verification
  61 Test Response Compaction and ATPG
  62 Placement
  100 Decision-Making for Complex SoCs in Consumer Electronic Products
  150 Tradeoffs and Choices for Emerging SoCs in High-End Applications